| A Resilient and Hierarchical IoT-Based Solution for Stress Monitoring in Everyday Settings | 0 | 0.34 | 2022 |
| AI-Driven Data Monetization: The Other Face of Data in IoT-Based Smart and Connected Health | 0 | 0.34 | 2022 |
| The convergence of IoT and distributed ledger technologies (DLT): Opportunities, challenges, and solutions | 2 | 0.36 | 2021 |
| Harnessing the Power of Smart and Connected Health to Tackle COVID-19: IoT, AI, Robotics, and Blockchain for a Better World | 0 | 0.34 | 2021 |
| Towards IoT-enabled Multimodal Mental Stress Monitoring | 0 | 0.34 | 2020 |
| Human Activity Recognition: From Sensors to Applications | 1 | 0.41 | 2020 |
| Towards Safer Roads: A Deep Learning-Based Multimodal Fatigue Monitoring System | 0 | 0.34 | 2020 |
| Towards fog-driven IoT eHealth: Promises and challenges of IoT in medicine and healthcare. | 61 | 2.11 | 2018 |
| Keynote Paper: From EDA to IoT eHealth: Promises, Challenges, and Solutions. | 5 | 0.43 | 2018 |
| Internet-of-Things and big data for smarter healthcare: From device to architecture, applications and analytics. | 14 | 0.76 | 2018 |
| Guest Editorial: Alternative Computing and Machine Learning for Internet of Things. | 0 | 0.34 | 2017 |
| On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines | 3 | 0.45 | 2016 |
| Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection | 10 | 0.61 | 2015 |
| Re-using BIST for circuit aging monitoring | 1 | 0.35 | 2015 |
| Deadspace-aware Power/Ground TSV planning in 3D floorplanning | 0 | 0.34 | 2015 |
| On-line prediction of NBTI-induced aging rates | 6 | 0.50 | 2015 |
| Stress-aware P/G TSV planning in 3D-ICs | 1 | 0.35 | 2015 |
| P/G TSV planning for IR-drop reduction in 3D-ICs | 3 | 0.37 | 2014 |
| Adaptive Mitigation of Parameter Variations | 0 | 0.34 | 2014 |
| On-chip voltage-droop prediction using support-vector machines | 10 | 0.62 | 2014 |
| Chip Health Monitoring Using Machine Learning | 1 | 0.35 | 2014 |
| Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach | 15 | 0.61 | 2013 |
| Negative Bias Temperature Instability-Aware Instruction Scheduling: A Cross-Layer Approach | 10 | 0.47 | 2013 |
| Statistical analysis of BTI in the presence of process-induced voltage and temperature variations | 11 | 0.51 | 2013 |
| Instruction-set extension under process variation and aging effects | 4 | 0.38 | 2013 |
| Incorporating the impacts of workload-dependent runtime variations into timing analysis | 14 | 0.80 | 2013 |
| Aging-Aware Timing Analysis Considering Combined Effects Of Nbti And Pbti | 17 | 0.84 | 2013 |
| A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing | 4 | 0.44 | 2013 |
| Chip-level modeling and analysis of electrical masking of soft errors | 1 | 0.35 | 2013 |
| NBTI mitigation by optimized NOP assignment and insertion | 20 | 0.86 | 2012 |
| Adaptive fault-tolerant DVFS with dynamic online AVF prediction. | 4 | 0.38 | 2012 |
| Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions | 11 | 0.51 | 2012 |
| Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates | 6 | 0.49 | 2012 |
| Modeling and estimation of power supply noise using linear programming | 7 | 0.53 | 2011 |
| A linear programming approach for minimum NBTI vector selection | 4 | 0.45 | 2011 |
| Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage Scaling | 2 | 0.39 | 2011 |
| An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects | 15 | 0.80 | 2011 |
| Reliability-Aware Dynamic Voltage and Frequency Scaling | 4 | 0.40 | 2010 |
| Instruction reliability analysis for embedded processors | 8 | 0.68 | 2010 |
