Paper Info
Title
Zamlog: a parallel algorithm for fault simulation based on Zambezi
Abstract
We present a new multiprocessor sequential circuit fault simulator, Zamlog, based on a novel uniprocessor simulator, Zambezi. Both the fault and test sets are partitioned for multiprocessor simulation. The parallelization technique, designed to preserve the efficiency of Zambezi, is simple to implement and has low communication requirements. Experimental results indicate that Zamlog can obtain speedups of up to 95. The speedups obtained and the scalability are between 3 and 10 times better than any reported in the literature. Furthermore, the speed-ups obtained are with respect to a uniprocessor algorithm which is superior, by an average of 40%, to those used to gauge the speed-ups of previous parallel systems.
Year
DOI
Venue
1996
10.1145/244522.244874
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Keywords
Field
DocType
parallel algorithm,zamlog,uniprocessor algorithm,novel uniprocessor simulator,fault simulator,new multiprocessor sequential circuit,low communication requirement,parallelization technique,uniprocessor simulator,previous parallel system,logic testing,test set,zambezi,fault simulation,sequential circuit fault simulator,test sets,multiprocessor simulation,parallel systems,sequential circuits,parallel algorithms
Uniprocessor system,Sequential logic,Computer science,Parallel algorithm,Logic testing,Parallel computing,Multiprocessing,Real-time computing,Fault Simulator,Gauge (firearms),Scalability
Conference
ISSN
ISBN
Citations 
1063-6757
0-8186-7597-7
3
PageRank 
References 
Authors
0.57
8
2
Name
Order
Citations
PageRank
Minesh B. Amin116210.36
Bapiraju Vinnakota223725.36