Name
Abstract | ||
|---|---|---|
In this paper, we describe an automatic place and route strategy for a high-density, super-regular, double-gate, transistor-array-based layout. Interconnects on all metal layers are strictly parallel and can be manufactured by an optical proximity correction free process. Our objective is to achieve a circuit layout area equal to the transistor footprint. Such layout constraints limit routing flexibility and render traditional approaches impractical. Our tools automatically generate circuits with several tens of transistors. Experimental results demonstrate both the efficiency of the proposed algorithms and the high quality of the layouts produced. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCAD.2009.2035580 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Design for manufacturability,circuit layout area,integrated circuit interconnections,layout constraint,network routing,transistor-array-based layout,route strategy,circuit layout,transistor layout,high quality,metal layer,layout generator,metal layers,automatic place,double-gate transistor-array-based layout,regular fabric,proposed algorithm,free process,transistor-level high-density regular circuits,optical proximity correction,integrated circuit layout,routing flexibility,optical proximity correction free process,interconnects,placement and routing,transistor footprint,transistor-level high-density regular circuit | Journal | 29 |
Issue | ISSN | Citations |
2 | 0278-0070 | 9 |
PageRank | References | Authors |
0.80 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yi-wei Lin | 1 | 52 | 5.22 |
| Malgorzata Marek-Sadowska | 2 | 2272 | 213.72 |
| Wojciech Maly | 3 | 1976 | 352.57 |