Name
Abstract | ||
|---|---|---|
The TSVM is a logical structured memory with a synchronizationto improve a performance in a multi-threadedparallel processing. The physical TSVM is realized bythe TSVM cache (TC) and a conventional memory in aMultiprocessor-on-a-chip (MOC) system. The L1 cache in aCPU consists of the TC, the General variable cache (GVC),and the instruction cache. The IYA (IY architecture) that isa new architecture divides a conventional data cache intothe TC and GVC. The TC caches the shared variables witha synchronization, and the GVC caches other general variables.Regardless of a CPU core, a MOC with the IYA canutilize parallelisms from the instruction level and the statementlevel to the thread level systematically. To estimatethe effect of the TC, preliminary experiments are performedon the multi-chip multiprocessor including the stand-aloneTSVM. The result shows that the TSVM cache improves theperformance. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ICPADS.2002.1183382 | ICPADS |
Keywords | Field | DocType |
bythe tsvm cache,iy architecture,iya canutilize parallelism,tsvm cache,intothe tc,shared memory,gvc cache,general variable cache,physical tsvm,l1 cache,instruction cache,synchronisation,parallel processing,chip | Computer architecture,Cache-oblivious algorithm,Cache pollution,Computer science,CPU cache,Cache,MESI protocol,Parallel computing,Cache algorithms,Cache coloring,Bus sniffing | Conference |
ISBN | Citations | PageRank |
0-7695-1760-9 | 2 | 0.44 |
References | Authors | |
4 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Akira Yamawaki | 1 | 17 | 9.36 |
| Masahiko Iwane | 2 | 13 | 3.79 |