Paper Info
Title
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains
Abstract
This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-on capture (LOC) scheme followed by the one-hot LOC scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large test sets. The proposed hybrid technique is intended to reduce test pattern count with acceptable ATPG runtime for multi-million-gate scan designs. In case the scan design contains multiple synchronous clock domains, each group of synchronous clock domains is treated as a clock group and tested using a launch aligned or a capture aligned LOC scheme. By combining these schemes together, we found the pattern counts for two large industrial designs were reduced by approximately 1.1X to 2.1X, while the ATPG runtime was increased by 10% to 50%, when compared to the one-hot clocking scheme alone.
Year
DOI
Venue
2011
10.1109/TCAD.2010.2092510
IEEE Trans. on CAD of Integrated Circuits and Systems
Keywords
DocType
Volume
one-hot clocking scheme,LOC scheme,Testing Scan Designs,acceptable ATPG runtime,asynchronous clock domain,one-hot scheme,short ATPG runtime,one-hot LOC scheme,Asynchronous Clock Domains,clock group,staggered scheme,ATPG runtime
Journal
30
Issue
ISSN
Citations 
3
0278-0070
0
PageRank 
References 
Authors
0.34
0
12
Name
Order
Citations
PageRank
Shianling Wu116526.85
Laung-terng Wang260144.22
Xiaoqing Wen379077.12
Zhigang Jiang48520.12
Lang Tan500.34
Yu Zhang600.34
Yu Hu753776.69
Wen-Ben Jone841946.30
M. S. Hsiao912411.32
James Chien-Mo Li1018727.16
Jiun-Lang Huang1126335.90
Lizhen Yu12122.89