Name
Abstract | ||
|---|---|---|
Due to physical defects or process variations, a logic circuit may fail to operate at the desired clock speed. So, verifying the timing behavior of digital circuits is always necessary, and needs to test for delay faults. When a delay fault has been detected, a specific diagnostic method is required to locate the site of the fault in the circuit. So, a reliable method for delay fault diagnosis is proposed in this paper. Firstly, we present the basic diagnostic method for delay faults, which is based on multivalued simulation and critical path tracing. Next, heuristics are given that decrease the number of critical paths and improve diagnosis results. In the second part of this paper, we provide an approximate method to refine the results obtained with the basic diagnostic process. We compute the detection threshold of the potential delay faults, and use statistical studies to classify the faults from the most likely to be the cause of failure to the less likely. Finally, results obtained with ISCAS'85 circuits are presented to show the effectiveness of the method. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1007/BF00996437 | J. Electronic Testing |
Keywords | Field | DocType |
combinational faulty circuit,critical path tracing,diagnosis,delay fault,simulation,advanced diagnostic method,critical path,digital circuits,process variation | Stuck-at fault,Digital electronics,Logic gate,Computer science,Electronic engineering,Real-time computing,Heuristics,Electronic circuit,Critical path tracing,Clock rate | Journal |
Volume | Issue | ISSN |
6 | 3 | 1573-0727 |
Citations | PageRank | References |
11 | 1.32 | 18 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Girard | 1 | 478 | 41.91 |
| C. Landrault | 2 | 11 | 1.32 |
| S. Pravossoudovitch | 3 | 689 | 54.12 |