Name
Abstract | ||
|---|---|---|
As fabrication process exploits even deeper submicron technology, global interconnect delay is becoming one of the most critical performance obstacles in system-on-chip (SoC) designs nowadays. Recent years latency-insensitive system (LIS), which enables multicycle communication to tolerate variant interconnect delay without substantially modifying pre-designed IP cores, has been proposed to conquer this issue. However, imbalanced interconnect latency and communication back-pressure residing in an LIS still degrade system throughput. In this paper, we present a throughput optimization technique with minimal queue insertion. We first model a given LIS as a quantitative graph (QG), which can be further compacted using the proposed techniques, so that much bigger problems can be handled. On top of QG, the optimal solution with minimal queue size can be achieved through integer linear programming based on the proposed constraint formulation in an acceptable runtime. The experimental results show that our approach can deal with moderately large systems in a reasonable runtime and save about 28% of queues compared to the prior art. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASPDAC.2011.5722257 | ASP-DAC |
Keywords | Field | DocType |
minimal queue insertion,multicycle communication,proposed constraint formulation,communication back-pressure,degrade system throughput,proposed technique,global interconnect delay,latency-insensitive system,acceptable runtime,submicron technology,integer programming,quantitative graph,linear programming,integer linear programming,system-on-chip,large system,minimal queue size,lis,logic design,qg,graph theory,variant interconnect delay,throughput optimization,soc design,optimization,system on chip,system on a chip,routing,throughput,compaction | Logic synthesis,System on a chip,Latency (engineering),Computer science,Queue,Rectilinear Steiner tree,Electronic engineering,Real-time computing,Integer programming,Linear programming,Throughput | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-7515-5 | 2 |
PageRank | References | Authors |
0.37 | 15 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Juinn-Dar Huang | 1 | 270 | 27.42 |
| Yi-Hang Chen | 2 | 9 | 1.00 |
| Ya-Chien Ho | 3 | 2 | 0.37 |