Name
Title | ||
|---|---|---|
A 1.25-Gb/S Burst-Mode Half-Rate Clock And Data Recovery Circuit Using Realigned Oscillation |
Abstract | ||
|---|---|---|
In this letter, a 1.25-Gb/s 0.18-mu m CMOS half-rate burst-mode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.4 x 1.4 mm(2), and power consumption is 32 mW under a 1.8-V supply voltage. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1093/ietele/e90-c.1.196 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
burst-mode CDR, clock recovery, phase-locked loop, realigned oscillation | Phase-locked loop,Clock recovery,Burst mode (photography),Half Rate,Delay-locked loop,Clock domain crossing,Electronic engineering,CMOS,Jitter,Engineering | Journal |
Volume | Issue | ISSN |
E90C | 1 | 1745-1353 |
Citations | PageRank | References |
2 | 0.47 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ching-Yuan Yang | 1 | 227 | 36.15 |
| Jung-Mao Lin | 2 | 28 | 4.52 |