Paper Info
Title
Making good points: application-specific pareto-point generation for design space exploration using statistical methods
Abstract
Field-programmable gate arrays (FPGAs) commonly implement system architectures composed from soft-core configurable components, such as a cache with configurable size or associativity, a processor with configurable datapath units, or a configurable network-on-chip connecting dozens of processors. Configurable components increasingly exist even on pre-fabricated platforms. Tuning configurable components to the particular application running on the architecture and to particular design constraints represents a challenging task often left to a designer. Knowledge of the Pareto-optimal points of a system for particular applications can be of benefit to designers seeking to make appropriate design tradeoffs for given constraints. Previous methods for generating Pareto points required extensive knowledge of an architecture's parameter interdependencies, used a simplistic approach that failed to find many parameters, or used randomized search algorithms that may have long runtimes. We introduce an algorithm for finding Pareto points, based on statistically rigorous methods derived from the Design of Experiments paradigm and extended for the purpose of finding Pareto points. The resulting DoE-based Pareto point Generator, or DPG, algorithm finds thorough Pareto points while running 3 times faster than randomized search algorithms, without requiring designer knowledge of parameter interdependencies--in fact, the approach determines those interdependencies automatically, representing an added bonus. We demonstrate DPG on Platune's configurable processor-bus-cache system-on-chip, Noxim's configurable network-on-chip, and the configurable Microblaze FPGA processor.
Year
DOI
Venue
2009
10.1145/1508128.1508149
FPGA
Keywords
Field
DocType
configurable processor-bus-cache system-on-chip,configurable size,good point,soft-core configurable component,parameter interdependency,design space exploration,application-specific pareto-point generation,particular application,configurable network-on-chip,pareto point,configurable datapath unit,statistical method,randomized search algorithm,configurable microblaze fpga processor,system architecture,design of experiment,random search,exploration,network on chip,system on chip,design of experiments,speedup,field programmable gate array,fpga,pruning
MicroBlaze,Datapath,Search algorithm,Computer science,Cache,Parallel computing,Field-programmable gate array,Real-time computing,Design space exploration,Pareto principle,Speedup
Conference
Citations 
PageRank 
References 
7
0.49
9
Authors
2
Name
Order
Citations
PageRank
David Sheldon1565.42
Frank Vahid22688218.00