Name
Abstract | ||
|---|---|---|
In recent high-density and low-power VLSIs, soft errors occurring on not only memory systems and the latches of logic circuits but also the combinational parts of logic circuits seriously affect the operation of systems. The conventional soft error tolerant methods for soft errors on the combinational parts do not provide enough high soft error tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and pass transistors. The paper also presents construction of soft error masking latches (SEM-Latches) capable of masking transient pulses occurring on combinational circuits. Moreover, experimental results show that the proposed method has higher soft error tolerant capability than the existing methods. For driving voltage VDD=3.3V, the proposed method is capable of masking transient pulses of magnitude 4.0V or less. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/DFT.2006.60 | DFT |
Keywords | Field | DocType |
higher soft error tolerant,high soft error tolerant,transient pulse,schmitt trigger circuit,soft error masking,conventional soft error tolerant,soft error masking circuit,soft error,logic circuit,combinational part,combinational circuit,fault tolerance,vlsi,low power electronics,logic circuits,combinational circuits | Logic gate,Masking (art),Soft error,Computer science,Schmitt trigger,Electronic engineering,Real-time computing,Combinational logic,Electronic circuit,Electrical engineering,Very-large-scale integration,Low-power electronics | Conference |
ISSN | ISBN | Citations |
1550-5774 | 0-7695-2706-X | 30 |
PageRank | References | Authors |
2.32 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoichi Sasaki | 1 | 30 | 2.32 |
| Kazuteru Namba | 2 | 114 | 27.93 |
| Hideo Ito | 3 | 100 | 17.45 |