Name
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/3DIC.2012.6263041 | 3DIC |
Keywords | Field | DocType |
testing,logic gates,cmos integrated circuits | Boundary scan,Discrete circuit,Circuit extraction,Circuit design,Electronic engineering,Engineering,Mixed-signal integrated circuit,Electronic circuit,Small Outline Integrated Circuit,Electrical engineering,Diode-or circuit | Conference |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Widianto | 1 | 0 | 0.34 |
| Hiroyuki Yotsuyanagi | 2 | 70 | 19.04 |
| Akira Ono | 3 | 0 | 0.34 |
| Masao Takagi | 4 | 0 | 0.34 |
| Masaki Hashizume | 5 | 98 | 27.83 |