Name
Abstract | ||
|---|---|---|
High performance compilers increasingly rely on accurate modeling of the machine resources to efficiently exploit the instruction level parallelism of an application. In this paper, we propose a reduced machine description that results in faster detection of resource contentions while preserving the scheduling constraints present in the original machine description. The proposed approach reduces a machine description in an automated, error-free, and efficient fashion, Moreover, it fully supports schedulers that backtrack and process operations in arbitrary order. Reduced descriptions for the DEC Alpha 21064, MIPS R3000/R3010, and Cydra 5 result in 4 to 7 times faster detection of resource contentions and require 22 to 90% of the memory storage used by the original machine descriptions. Precise measurement for the Cydra 5 indicates that reducing the machine description results in a 2.9 times faster contention query module. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1145/231379.231386 | PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation |
Field | DocType | Volume |
Instruction-level parallelism,Programming language,Computer science,Scheduling (computing),Parallel computing,Compiler,Exploit,Real-time computing,Theoretical computer science,DEC Alpha | Conference | 31 |
Issue | ISSN | ISBN |
5 | 0362-1340 | 0-89791-795-2 |
Citations | PageRank | References |
15 | 1.53 | 16 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexandre E. Eichenberger | 1 | 427 | 46.67 |
| Edward S. Davidson | 2 | 922 | 171.30 |