Title
Information theoretic and security analysis of a 65-nanometer DDSLL AES S-box
Abstract
In a recent work from Eurocrypt 2011, Renauld et al. discussed the impact of the increased variability in nanoscale CMOS devices on their evaluation against side-channel attacks. In this paper, we complement this work by analyzing an implementation of the AES S-box, in the DDSLL dual-rail logic style, using the same 65-nanometer technology. For this purpose, we first compare the performance results of the static CMOS and dual-rail S-boxes. We show that full custom design allows to nicely mitigate the performance drawbacks that are usually reported for dual-rail circuits. Next, we evaluate the side-channel leakages of these S-boxes, using both simulations and actual measurements. We take advantage of state-of-the-art evaluation tools, and discuss the quantity and nature (e.g. linearity) of the physical information they provide. Our results show that the security improvement of the DDSLL S-box is typically in the range of one order of magnitude (in terms of "number of traces to recover the key"). They also confirm the importance of a profiled information theoretic analysis for the worst-case security evaluation of leaking devices. They finally raise the important question whether dual-rail logic styles remain a promising approach for reducing the side-channel information leakages in front of technology scaling, as hardware constraints such as balanced routing may become increasingly challenging to fulfill, as circuit sizes tend towards the nanometer scale.
Year
Venue
Keywords
2011
CHES
dual-rail logic style,dual-rail s-boxes,65-nanometer ddsll aes s-box,information theoretic analysis,state-of-the-art evaluation tool,side-channel attack,side-channel leakage,security analysis,dual-rail circuit,physical information,side-channel information leakage,ddsll dual-rail logic style
Field
DocType
Volume
S-box,Information leakage,Computer science,Physical information,Theoretical computer science,Full custom,CMOS,Security analysis,Electronic circuit,Current-mode logic
Conference
6917
ISSN
Citations 
PageRank 
0302-9743
13
0.66
References 
Authors
25
4
Name
Order
Citations
PageRank
Mathieu Renauld12259.80
Dina Kamel21188.58
François-Xavier Standaert33070193.51
Denis Flandre431670.47