Name
Affiliation
Papers
DENIS FLANDRE
universite catholique de louvain
72
Collaborators
Citations 
PageRank 
118
316
70.47
Referers 
Referees 
References 
829
584
268
Search Limit
100829
Title
Citations
PageRank
Year
Performances Evaluation of On-Chip Large-Size-Tapped Transformer for MEMS Applications00.342020
Analysis, Modeling, and Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT Smart Sensors.60.502019
Self-Heating in 28 FDSOI UTBB MOSFETs at Cryogenic Temperatures00.342019
A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer00.342018
A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks.00.342018
Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI00.342018
Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors00.342018
A Transient Noise Analysis of Secured Dual-Rail Based Logic Style00.342018
Let'S Make It Noisy: A Simulation Methodology For Adding Intrinsic Physical Noise To Cryptographic Designs00.342018
Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits.00.342018
Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis.00.342018
Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics00.342018
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation.00.342017
Multiple-Wavelength Detection in SOI Lateral PIN Diodes With Backside Reflectors.00.342017
Automated Design of a 13.56 MHz 19µW Passive Rectifier With 72% Efficiency Under 10µA load.00.342016
A 16×16 CMOS Capacitive Biosensor Array Towards Detection of Single Bacterial Cell.00.342016
Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors.00.342016
CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array.00.342016
Automated design of a 13.56 MHz corner-robust efficient differential drive rectifier for 10 μA load.00.342016
Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers.00.342016
Analysis And Optimization For Dynamic Read Stability In 28nm Sram Bitcells00.342015
A 0.48mm² 5µW-10mW Indoor-Outdoor PV Energy-Harvesting Management Unit in a 65nm SoC based on a Single Bidirectional Multi-Gain/Multi-Mode Switched-Cap Converter with Supercap Storage00.342015
A Capacitance-to-Frequency Converter With On-Chip Passivated Microelectrodes for Bacteria Detection in Saline Buffers Up to 575 MHz30.472015
Wide band study of silicon-on-insulator photodiodes on suspended micro-hotplates platforms10.632015
A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs00.342015
A 65 Nm Cmos Ultra-Low-Power Impulse Radio-Ultra-Wideband Emitter For Short-Range Indoor Localization10.372015
A Self-Oscillating System to Measure the Conductivity and the Permittivity of Liquids within a Single Triangular Signal10.542014
A Sizing Methodology for On-Chip Switched-Capacitor DC/DC Converters50.602014
Understanding the limitations and improving the relevance of SPICE simulations in side-channel security evaluations.10.352014
Variability of UTBB MOSFET analog figures of merit in wide frequency range00.342014
SleepWalker: A 25-MHz 0.4-V Sub-mm2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes.00.342013
Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs.00.342013
Threshold voltage extraction techniques and temperature effect in context of global variability in UTBB mosfets.00.342013
Validation of a Novel ultra-thin silicon Strip Detector for Hadron Therapy beam Monitoring.00.342013
Pushing Adaptive Voltage Scaling Fully On Chip00.342012
On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime.10.412012
Design Of An Ultra-Low-Power Multi-Stage Ac/Dc Voltage Rectifier And Multiplier Using A Fully-Automated And Portable Design Methodology10.412012
High-energy neutrons effect on strained and non-strained SOI MuGFETs and planar MOSFETs.00.342012
Information theoretic and security analysis of a 65-nanometer DDSLL AES S-box130.662011
Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags100.712011
A formal study of power variability issues and side-channel attacks for nanoscale devices582.152011
Characterization and modelling of single event transients in LDMOS-SOI FETs.00.342011
Fully-Automated and Portable Design Methodology for Optimal Sizing of Energy-Efficient CMOS Voltage Rectifiers41.162011
ULPFA: a new efficient design of a power-aware full adder110.732010
Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic---Mitigation at Technology and Circuit Levels10.412010
Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits50.462010
Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits20.422010
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic111.242009
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits201.272009
Scaling Trends Of The Aes S-Box Low Power Consumption In 130 And 65 Nm Cmos Technology Nodes80.632009
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