Name
Title | ||
|---|---|---|
An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs |
Abstract | ||
|---|---|---|
The importance of dynamic thread scheduling is increasing with the emergence of Asymmetric Multicore Processors (AMPs). Since the computing needs of a thread often vary during its execution, a fixed thread-to-core assignment is sub-optimal. Reassigning threads to cores (thread swapping) when the threads start a new phase with different computational needs, can significantly improve the energy efficiency of AMPs. Although identifying phase changes in the threads is not difficult, determining the appropriate thread-to-core assignment is a challenge. Furthermore, the problem of thread reassignment is aggravated by the multiple power states that may be available in the cores. To this end, we propose a novel technique to dynamically assess the program phase needs and determine whether swapping threads between core-types and/or changing the voltage/frequency levels (DVFS) of the cores will result in higher throughput/Watt. This is achieved by predicting the expected throughput/Watt of the current program phase at different voltage/frequency levels on all the available core-types in the AMP. We show that the benefits from thread swapping and DVFS are orthogonal, demonstrating the potential of the proposed scheme to achieve significant benefits by seamlessly combining the two. We illustrate our approach using a dual-core High-Performance (HP)/Low-Power (LP) AMP with two power states and demonstrate significant throughput/Watt improvement over different baselines. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/PACT.2013.6618804 | PACT |
Keywords | Field | DocType |
asymmetric multicore processor (amp),throughput maximization,phase detection,processor scheduling,new phase,power aware computing,asymmetric multicore processors,dual-core low-power amp,watt maximization,frequency levels,reassigning thread,multiple power states,dual-core high-performance amp,watt improvement,amp,multiprocessing systems,throughput/watt prediction,hardware performance counters (hpcs),opportunistic prediction-based thread scheduling,computational needs,phase change identification,program phase need,dvfs,different baselines,thread reassignment,current program phase,voltage levels,phase change,dynamic thread scheduling,thread swapping,fixed thread-to-core assignment,energy efficiency improvement,frequency level | Thread scheduling,Computer science,Efficient energy use,Parallel computing,Voltage,Watt,Thread (computing),Real-time computing,Throughput,Phase detector,Multi-core processor,Embedded system | Conference |
ISSN | ISBN | Citations |
1089-795X | 978-1-4799-1018-2 | 12 |
PageRank | References | Authors |
0.64 | 23 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arunachalam Annamalai | 1 | 84 | 5.67 |
| R. Rodrigues | 2 | 111 | 10.56 |
| Israel Koren | 3 | 1579 | 175.07 |
| Sandip Kundu | 4 | 1103 | 137.18 |