Paper Info
Title
Abstract: Exploring Design Space of a 3D Stacked Vector Cache
Abstract
Although 3D integration technologies with through silicon vias (TSVs) have expected to overcome the memory and power wall problems in the future microprocessor design, there is no promising EDA tools to design 3D integrated VLSIs. In addition, effects of 3D integration on microprocessor design have not been discussed well. Under this situation, this paper presents design approach of 3D stacked cache memories using existing EDA tools, and shows early performances evaluation of 3D stacked cache memories for vector processors.
Year
DOI
Venue
2012
10.1109/SC.Companion.2012.270
SC Companion
Keywords
Field
DocType
exploring design space,cache memory,early performances evaluation,power wall problem,integrated vlsis,promising eda tool,microprocessor design,existing eda tool,future microprocessor design,design approach,integration technology,stacked vector cache,electronic design automation
Design space,Computer architecture,Computer science,Cache,Parallel computing,Electronic design automation,Microprocessor design
Conference
Citations 
PageRank 
References 
0
0.34
0
Authors
5
Name
Order
Citations
PageRank
Ryusuke Egawa110928.68
Jubee Tada274.69
Yusuke Endo300.68
Hiroyuki Takizawa427346.54
Hiroaki Kobayashi510814.52