Name
Abstract | ||
|---|---|---|
Multigigabit LDPC decoders are demanded by standards like IEEE 802.15.3c and IEEE 802.11ad. To achieve the high throughput while supporting the needed flexibility, sophisticated architectures are mandatory. This paper comprehensively presents the design space for flexible multigigabit LDPC applications for the first time. The influence of various design parameters on the hardware is investigated in depth. Two new decoder architectures in a 65nm CMOS technology are presented to further explore the design space. In the past, the memory domination was the bottleneck for throughputs of up to 1Gbit/s. Our systematic investigation of column- versus row-based partially parallel decoders shows that this is no more a bottleneck for multigigabit architectures. The evolutionary progress in flexible multigigabit LDPC decoder design is highlighted in an extensive comparison of state-of-the-art decoders. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1155/2012/942893 | VLSI Design |
Keywords | Field | DocType |
multigigabit architecture,various design parameter,multigigabit ldpc decoder,design space,decoders shows,state-of-the-art decoder,flexible multigigabit ldpc application,new decoder architecture,flexible multigigabit ldpc decoder,cmos technology | Design space,Bottleneck,Low-density parity-check code,Computer science,Electronic engineering,CMOS,Throughput | Journal |
Volume | ISSN | Citations |
2012, | 1065-514X | 9 |
PageRank | References | Authors |
0.70 | 9 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Philipp Schläfer | 1 | 26 | 3.34 |
| Christian Weis | 2 | 284 | 26.11 |
| Norbert Wehn | 3 | 1165 | 137.17 |
| Matthias Alles | 4 | 102 | 7.17 |