Title
An All-Digital Clock Recovery Architecture For The Bran Hiperaccess Uplink Receiver
Abstract
In this work, an all-digital synchronization recovery circuit is proposed for the uplink scheme of the ETSI BRAN Hiperaccess receiver. In particular a fast, open-loop algorithm, which exploits the TDMA burst preamble made of 16 or 32 cazac symbols, is tested by means of a link-level simulator operating at twice the symbol rate. At the receiver we suppose to use a fixed local oscillator and the symbol timing recovery is performed by means of digital interpolation. The fractional delay parameter for a fourth and sixth order Farrow interpolator is computed by means of a second order polynomial representation of the maximum likelihood function. After the recovery of the symbol timing, the phase offset is adjusted by simply taking the argument of the log-likelihood function. Performances of the proposed architecture are evaluated by measuring the symbol error rate and the synchronization error variances on AWGN channel.
Year
DOI
Venue
2006
10.1109/VETECS.2006.1683248
2006 IEEE 63RD VEHICULAR TECHNOLOGY CONFERENCE, VOLS 1-6
Keywords
Field
DocType
maximum likelihood,synchronization,maximum likelihood estimation,time division multiple access,second order,likelihood function,local oscillator,interpolation,log likelihood function,radio receivers,synchronisation,computational modeling,maximum likelihood function
Synchronization,Symbol rate,Computer science,Communication channel,Electronic engineering,Digital clock,Time division multiple access,Additive white Gaussian noise,Local oscillator,Telecommunications link
Conference
ISSN
Citations 
PageRank 
1550-2252
3
0.46
References 
Authors
0
3
Name
Order
Citations
PageRank
Pietro Savazzi18316.09
Paolo Gamba268292.97
Sergio Callegari311218.52