Paper Info
Title
Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors
Abstract
The performance of the various cache coherence protocols proposed in the literature have been extensively analyzed in the context of high-performance multi-processor systems.A similar analysis for Multi-Processor Systems-on-Chips (MP-SoCs), where energy is at least as important as performace, and for which strict constraints on hardware and software resources do exist, has not been done yet.This work provides an effort in that sense, showing energy/performance tradeoffs for different snoop-based protocols on a realistic MPSoC architecture. The analysis leverage a multi-processor simulation platform, augmented with accurate power models, that allows cycle-accurate simulations.Our analysis show that (i) cache write policy is actually more important than the actual cache coherence protocol, and (ii) matching the programming model and style to the architecture may have dramatic effects on the energy and performance of the system.
Year
DOI
Venue
2005
10.1145/1057661.1057728
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
single-chip multi-processors,realistic mpsoc architecture,similar analysis,analysis leverage,multi-processor simulation platform,high-performance multi-processor system,multi-processor systems-on-chips,performance tradeoffs,actual cache coherence protocol,various cache coherence protocol,analysis show,energy efficiency,multiprocessor,programming model,system on chip,cache coherence,energy efficient
Computer architecture,Cache invalidation,Cache pollution,Computer science,Cache,MESI protocol,Real-time computing,Cache algorithms,Cache coloring,Bus sniffing,Smart Cache,Embedded system
Conference
ISBN
Citations 
PageRank 
1-59593-057-4
14
0.82
References 
Authors
18
4
Name
Order
Citations
PageRank
Mirko Loghi121817.83
Martin Letis2140.82
Luca Benini3131161188.49
Massimo Poncino446057.48