Name
Abstract | ||
|---|---|---|
As the VLSI manufacturing technology shrinks to 65 nm and below, reducing the yield loss induced by via failures is a critical issue in design for manufacturability (DFM). Semiconductor foundries highly recommend using the double-via insertion (DVI) method to improve yield and reliability of designs. This work applies the DVI method in the post-stage of an X-architecture clock routing for double-via insertion rate improvement. The proposed DVI-X algorithm constructs the bipartite graphs of the partitioned clock routing layout with single vias and redundant-via candidates (RVCs). Then, DVI-X applies the augmenting path approach associated with the construction of the maximal cliques to obtain the matching solution from the bipartite graphs. Experimental results on benchmarks show that DVI-X can achieve higher double-via insertion rate by 3% and less running time by 68% than existing works. Moreover, a skew tuning technique is further applied to achieve zero skew because the inserted double vias affect the clock skew. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1587/transfun.E94.A.706 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | DocType | Volume |
clock routing, design for manufacturability, double via, X-architecture | Journal | E94A |
Issue | ISSN | Citations |
2 | 0916-8508 | 0 |
PageRank | References | Authors |
0.34 | 11 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chia-chun Tsai | 1 | 109 | 23.04 |
| Chung-chieh Kuo | 2 | 10 | 3.28 |
| Trong-yen Lee | 3 | 98 | 20.70 |