Name
Abstract | ||
|---|---|---|
This paper presents a non-scan design-for-test-ability method for controllers that are synthesized from FSMs (Finite State Machines). The proposed method can achieve complete fault efficiency: test patterns for a combinational circuit of a controller are applied to the controller using state transitions of the FSM. lit the proposed method, at-speed test application can be performed and the test application time is shorter than previous methods. Moreover, experimental results show the area overhead is low. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ATS.1998.741615 | Asian Test Symposium |
Keywords | Field | DocType |
complete fault efficiency,non-scan dft method,sequential circuits,finite state machine,design for testability,vlsi,sequential analysis,design methodology,state transition,registers,combinational circuits,combinational circuit,finite state machines | Design for testing,Automatic test pattern generation,Control theory,Sequential logic,Computer science,Automatic testing,Real-time computing,Finite-state machine,Electronic engineering,Combinational logic,Very-large-scale integration | Conference |
ISBN | Citations | PageRank |
0-8186-8277-9 | 11 | 0.86 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Satoshi Ohtake | 1 | 135 | 21.62 |
| Toshimitsu Masuzawa | 2 | 635 | 91.06 |
| Hideo Fujiwara | 3 | 36 | 4.64 |