Name
Abstract | ||
|---|---|---|
A sleep transistor P/G network synthesis method has been developed to address the requirements from industrial power-gating designs, where sleep transistors are custom designed with a fixed size and the optimal sleep transistor P/G network is achieved by simultaneously optimizing sleep transistor insertion and placement as well as the power network grids and wires for minimum area, maximum routeabillity with a given IR-drop target. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISQED.2007.22 | San Jose, CA |
Keywords | Field | DocType |
power network synthesis method,transistor insertion,industrial power gating designs,transistor p,ir-drop target,g network synthesis method,maximum routeabillity,industrial power-gating design,g network,sleep transistor p,power network grid,fixed size,design optimization,circuits,integrated circuit design,network synthesis,power mosfet,transistors,sleep,switches | Computer science,Network synthesis filters,Power MOSFET,Power network,Electronic engineering,Integrated circuit design,Power gating,Transistor,G-network,Electronic circuit,Electrical engineering | Conference |
ISBN | Citations | PageRank |
0-7695-2795-7 | 6 | 0.79 |
References | Authors | |
10 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kaijian Shi | 1 | 65 | 6.47 |
| Zhian Lin | 2 | 17 | 1.86 |
| Yimin Jiang | 3 | 335 | 35.50 |