Sleep Transistor Design In 28nm Cmos Technology | 0 | 0.34 | 2013 |
Automation Of Switch Insertion And Power Network Generation In 28 Nm Power-Switched Designs | 0 | 0.34 | 2012 |
Well tapping methodologies in power-gating design | 0 | 0.34 | 2011 |
Low-power SOC implementation: What you need to know. | 0 | 0.34 | 2010 |
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs | 11 | 0.74 | 2008 |
A Power Network Synthesis Method for Industrial Power Gating Designs | 6 | 0.79 | 2007 |
Challenges in sleep transistor design and implementation in low-power designs | 47 | 2.85 | 2006 |
Virtual hierarchical design representations for distributed optimization of multi-million gate designs | 0 | 0.34 | 2005 |
Hybrid hierarchical timing closure methodology for a high performance and low power DSP | 1 | 0.40 | 2003 |