Paper Info
Title
QDI latches characteristics and asynchronous linear-pipeline performance analysis
Abstract
Asynchronous logic is a hot topic due to its interesting features of power saving, low noise and robustness to parameters variations. However, its performance analysis is relatively complex. In fact, the handshaking protocol strongly influences the performance of the pipelined architectures. This paper introduces verified Standard-Logic schematics for QDI asynchronous latches and analyzes their characteristics. Buffering capacity and protocol gain are defined and analyzed. Based on this analysis, reduced performance equations are first introduced. By means of the dependency graphs, a new formal method is then proposed to analyze the performance of asynchronous linear-pipeline. This methodology is used to derive general equations for each latch type. Contrarily to previously proposed methods, this method can be applied to any asynchronous linear-pipeline without restrictions on its functional block delays. Therefore, the contributions of this paper enable the designers to understand the benefits brought by the different asynchronous latches, to compare them and make the right choice according to their design constrains....
Year
DOI
Venue
2006
10.1007/11847083_57
PATMOS
Keywords
Field
DocType
performance analysis,asynchronous logic,buffering capacity,new formal method,protocol gain,qdi asynchronous,handshaking protocol,different asynchronous,asynchronous linear-pipeline,asynchronous linear-pipeline performance analysis,reduced performance equation,formal method
Asynchronous communication,Asynchronous system,Computer science,Electronic engineering,Schematic,Robustness (computer science),Real-time computing,Handshaking,Formal methods,Dependency graph,Asynchronous circuit
Conference
Volume
ISSN
ISBN
4148
0302-9743
3-540-39094-4
Citations 
PageRank 
References 
8
0.67
4
Authors
2
Name
Order
Citations
PageRank
Eslam Yahya1255.94
Marc Renaudin249849.15