Paper Info
Title
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design
Abstract
With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip designers. Latency-insensitive design (LID) has been proposed as a "correct-by-construction" design methodology to cope with this problem. In this paper we present the design and implementation of a new class of interface circuits to support LID that offers substantial performance improvements with limited area overhead with respect to previous designs proposed in the literature. This claim is supported by the experimental results that we obtained completing semi-custom implementations of the three designs with a 90nm industrial standard-cell library. We also report on the formal verification of our design: using the NuSMV model checker we verified that the RTL synthesizable implementations of our LID interface circuits (relay stations and shells) are correct refinements of the corresponding abstract specifications according to the theory of LID.
Year
DOI
Venue
2007
10.1109/MEMCOD.2007.371256
MEMOCODE
Keywords
Field
DocType
new class,correct refinement,interface circuit,latency-insensitive design,design methodology,previous design,nusmv model checker,lid interface circuit,interface circuits,rtl synthesizable implementation,system-on-chip designer,corresponding abstract specification,system on chip,computer science,formal verification,integrated circuit design
System on a chip,Model checking,Computer science,Latency (engineering),Design methods,Implementation,Real-time computing,Integrated circuit design,Relay,Embedded system,Formal verification
Conference
ISBN
Citations 
PageRank 
1-4244-1050-9
16
0.65
References 
Authors
22
4
Name
Order
Citations
PageRank
Cheng-Hong Li1795.98
Rebecca Collins2160.65
Sampada Sonalkar3171.33
Luca P. Carloni41713120.17