Name
Abstract | ||
|---|---|---|
Dynamic reconfiguration for fine grained architec- tures is still associated with significant reconfiguration costs. In this paper we propose a new reconfiguration aware design flow. The tools in this flow implement a set of tasks concurrently. The flow leads to task im- plementations with minimal costs for routing reconfig- uration. This is mainly achieved by our mapping tool which solves two fundamental problems: Our mapping algorithm generates variants for the mapping of netlist cells to logic blocks. From those logic blocks a subset for each task is selected that minimizes the cost for routing reconfiguration. We derive a cost function and formu- late an integer linear program to solve this problem. We implemented several task sets with our method and compare the results to previous solutions. We show that the reconfiguration aware mapping leads to better re- sults than early approaches with vendor provided tools. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/IPDPS.2007.370385 | IPDPS |
Keywords | Field | DocType |
data mining,switches,design flow,routing,network routing,simultaneous localization and mapping,cost function,field programmable gate arrays,fpga,logic design | Logic synthesis,Integer,Netlist,Computer science,Parallel computing,Field-programmable gate array,Implementation,Design flow,Linear programming,Control reconfiguration,Distributed computing | Conference |
Citations | PageRank | References |
5 | 0.44 | 7 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Markus Rullmann | 1 | 27 | 3.82 |
| Renate Merker | 2 | 159 | 20.59 |