Name
Abstract | ||
|---|---|---|
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault (useless patterns). In order to reduce the test time, we can remove useless patterns or change them to useful patterns (fault dropping). In this paper, we reseed, modify the pseudo-random, and use an additional bit counter to improve test length and achieve high fault coverage. The fact is that a random test set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change them to useful patterns, and when the patterns change, we pick out the numbers with less bits, leading to very short test length. The technique we present is applicable for single-stuck-at faults. The seeds we use are deterministic so 100% fault coverage can be achieve. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISCAS.2005.1465253 | ISCAS (3) |
Keywords | Field | DocType |
bit counter,integrated circuit testing,test pattern generator,single-stuck-at faults,random number generation,vlsi testing,automatic test pattern generation,built-in self test,bist,test time reduction,built-in self-test,random test set,useless pattern removal,on-chip test logic,bit modifying logic,reseeding mechanism,pseudo-random pattern generator,pseudo-random testing,fault coverage,logic testing,fault detection,random testing,very large scale integration | Stuck-at fault,Automatic test pattern generation,Random testing,Fault coverage,Computer science,Algorithm,Electronic engineering,Random number generation,Test compression,Test set,Built-in self-test | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-8834-8 | 1 |
PageRank | References | Authors |
0.35 | 13 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiann-Chyi Rau | 1 | 13 | 6.75 |
| Ying-fu Ho | 2 | 2 | 0.74 |
| Po-han Wu | 3 | 482 | 31.49 |