Paper Info
Title
Power Efficiency of Application-Dependent Self-Configuring Pipeline Depth in DSP Microprocessors
Abstract
We illustrate the results of a simulation-based analysis of "self-configuring" pipeline depth inDSP computations, focusing on the effects on power efficiency. We use three different metrics for power efficiency: mips/watts, mips 2 /watts, and watts under an absolute performance constraint. Our results, based on a set of commercial DSP benchmarks, show that an application-dependent self-configuring pipeline depth significantly affects power efficiency.
Year
DOI
Venue
2003
10.1109/IPDPS.2003.1213342
IPDPS
Keywords
Field
DocType
different metrics,dsp microprocessors,commercial dsp benchmarks,power efficiency,simulation-based analysis,application-dependent self-configuring pipeline depth,pipeline depth indsp computation,absolute performance constraint,logic simulation,computer architecture,pipelines,digital signal processing,application software,computational modeling
Electrical efficiency,Digital signal processing,Computer science,Parallel computing,Logic simulation,Computation
Conference
ISBN
Citations 
PageRank 
0-7695-1926-1
0
0.34
References 
Authors
3
2
Name
Order
Citations
PageRank
Mauro Olivieri138536.09
Marco Raspa200.34