Name
Title | ||
|---|---|---|
Cycle-time-aware sequential way-access set-associative cache for low energy consumption |
Abstract | ||
|---|---|---|
In this paper, we exploit the concept of sequential way access to reduce the number of ways being activated on each access of set-associative cache for low energy consumption while maintaining performance. The proposed architecture accesses each way in sequence, and then eliminates subsequent accesses if a hit is detected. It features smart cache placement and replacement policies to minimize the number of required access cycles. It can also reduce the heavy fanout load of the hit-signal, which suppresses the possible increase of cache cycle time due to more complicated cache control mechanism. The experimental results show that a 32 KB 2-way sequential way-access set-associative cache reduces the energy consumption by 24% compared against a conventional 2-way set-associative cache with the same size at virtually no performance loss. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/APCCAS.2008.4746157 | APCCAS |
Keywords | Field | DocType |
memory size 32 kbyte,cache storage,smart cache replacement,smart cache placement,low energy consumption,content-addressable storage,cycle-time-aware sequential way-access set-associative cache,two-way sequential way-access set-associative cache,cycle time,multiplexing,computer architecture,memory management,energy efficiency | Cache-oblivious algorithm,Cache invalidation,Cache pollution,Cache,Computer science,Parallel computing,Cache algorithms,Page cache,Electronic engineering,Cache coloring,Smart Cache,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4244-2342-2 | 0 | 0.34 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chih-Hui Ting | 1 | 0 | 0.34 |
| Juinn-Dar Huang | 2 | 270 | 27.42 |
| Yu-Hsiang Kao | 3 | 44 | 2.76 |