Name
Abstract | ||
|---|---|---|
This work presents a frequency-scaling low-power (FSLP) design methodology for managing power consumption of cores in the tile-based network-on-chip (NOC) architecture. A moving picture experts group (MPEG) core is tested using the field-programmable gate array (FPGA) implementation to verify the feasibility of the proposed method. Measurement results show that about 30% power consumption can be saved in the MPEG core and reveal that the proposed FSLP design method can be suitable for cores in the tile-based NOC applications. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1093/ietfec/e88-a.12.3580 | IEICE Transactions |
Keywords | Field | DocType |
frequency-scaling approach,field-programmable gate array,power consumption,proposed fslp design method,tile-based noc application,mpeg core,design methodology,picture experts group,measurement result,tile-based network-on-chip | Computer architecture,Architecture,Field-programmable gate array,Theoretical computer science,Mpeg standards,Design methods,Gate array,Frequency scaling,Tile,Mathematics,Power consumption,Embedded system | Journal |
Volume | Issue | ISSN |
E88-A | 12 | 0916-8508 |
Citations | PageRank | References |
3 | 0.45 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chun-Lung Hsu | 1 | 59 | 14.53 |
| Wen-Tso Wang | 2 | 3 | 0.45 |
| Ying-Fu Hong | 3 | 3 | 0.45 |