Title
Low-power and area-efficient FIR filter implementation suitable for multiple taps
Abstract
This paper describes a 32-tap finite impulse response (FUR) filter with two 16-tap macros suitable for multiple taps. The derived condition for a coded coefficient and data block shows 35% savings in power consumption and 44% improvement in occupied area compared to a typical radix-4 modified Booth algorithm. According to the condition and separated shifting-accessing clock scheme, we have implemented a 32-tap FIR filter in 0.6-µm CMOS technology with three levels of metal. The chip that occupies 2.3 × 2.5 mm2 of silicon area has an operating frequency of 20 MHz and consumes 75 mW at Vdd = 3.3 V.
Year
DOI
Venue
2003
10.1109/TVLSI.2002.801570
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
multiple tap,operating frequency,silicon area,area-efficient fir filter implementation,32-tap finite impulse response,32-tap fir filter,16-tap macro,power consumption,m cmos technology,data block shows,occupied area,finite impulse response filter,vlsi,fir filters,very large scale integration,filtering,finite impulse response,silicon,capacitance,digital filter,chip,low power electronics,digital filters,indexing terms,frequency,fir filter,cmos technology
Digital filter,Computer science,Filter (signal processing),Electronic engineering,CMOS,Chip,Finite impulse response,Electrical engineering,Very-large-scale integration,Booth's multiplication algorithm,Low-power electronics
Journal
Volume
Issue
ISSN
11
1
1063-8210
Citations 
PageRank 
References 
7
0.97
2
Authors
2
Name
Order
Citations
PageRank
Kyung-Saeng Kim171.31
Kwyro Lee226570.73