Name
Abstract | ||
|---|---|---|
The skillful utilization of the memory structure of a processor and of its background memory may crucially affect the system performance. We propose a restructuring of for-loop programs by hierarchical partitioning which improves the properties of the algorithm with respect to the memory utilization. We consider the problem for regularly connected processor arrays (where single processors are a special case) and for a memory structure which is subdivided into local foreground memory (register) and background memory with up to three levels (cache, RAM, mass storage). The extension of the lifetime of a variable on an inner memory level, i.e. the decrease of the number of read accesses to more outer memory levels is the object of the proposed method. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/ISSS.1997.621679 | ISSS |
Keywords | Field | DocType |
local foreground memory,skillful utilization,$+,outer memory level,i,-,background memory,inner memory level,memory utilization,for-loop program,:,memory structure,processor array,single processor,background memory utilization,system performance,high level synthesis,ram,registers,difference equations,mass storage,cache,indexing | Registered memory,Interleaved memory,Shared memory,Computer science,Read-write memory,Parallel computing,Real-time computing,Memory management,Memory map,Computer memory,Auxiliary memory | Conference |
ISBN | Citations | PageRank |
0-8186-7949-2 | 0 | 0.34 |
References | Authors | |
9 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Uwe Eckhardt | 1 | 5 | 1.32 |
| Renate Merker | 2 | 159 | 20.59 |