Name
Abstract | ||
|---|---|---|
Error correcting codes are widely used in communication and storage applications. Codec complexity has usually been measured with a software implementation in mind. A recent hardware implementation of a Low Density Parity Check code (LDPC) indicates that interconnect complexity dominates the VLSI cost. We describe a heuristic interconnect-aware synthesis algorithm which generates LDPC codes that use an order of magnitude less wiring with little or no loss of coding efficiency. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/996566.996702 | DAC |
Keywords | Field | DocType |
coding efficiency,interconnect-efficient low density parity,software implementation,check code,low density parity check,ldpc code,codec complexity,storage application,heuristic interconnect-aware synthesis algorithm,vlsi cost,recent hardware implementation,error correction code,software measurement,very large scale integration,codecs,sparse matrices,turbo codes,application software,algorithms,decoding,hardware,routing,performance | Forward error correction,Algorithmic efficiency,Concatenated error correction code,Low-density parity-check code,Computer science,Turbo code,Parallel computing,Block code,Real-time computing,Very-large-scale integration,Codec | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-58113-828-8 | 7 |
PageRank | References | Authors |
0.57 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marghoob Mohiyuddin | 1 | 179 | 11.27 |
| Amit Prakash | 2 | 50 | 5.97 |
| Adnan Aziz | 3 | 1778 | 149.76 |
| Wayne Wolf | 4 | 7 | 0.57 |