Paper Info
Title
Increasing hardware efficiency with multifunction loop accelerators
Abstract
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally designed in a single-function manner, wherein each loop nest is implemented as a dedicated hardware block. This paper focuses on hardware sharing across loop nests by creating multifunction loop accelerators, or accelerators capable of executing multiple algorithms. A compiler-based system for automatically synthesizing multifunction loop accelerator architectures from C code is presented. We compare the effectiveness of three architecture synthesis approaches with varying levels of complexity: sum of individual accelerators, union of individual accelerators, and joint accelerator synthesis. Experiments show that multifunction accelerators achieve substantial hardware savings over combinations of single-function designs. In addition, the union approach to multifunction synthesis is shown to be effective at creating low-cost hardware by exploiting hardware sharing, while remaining computationally tractable.
Year
DOI
Venue
2006
10.1145/1176254.1176322
CODES+ISSS
Keywords
Field
DocType
multifunction loop accelerator,specialized hardware accelerator,loop nest,low-cost hardware,hardware efficiency,loop accelerator,critical application loop nest,individual accelerator,multifunction loop accelerator architecture,dedicated hardware block,hardware sharing,embedded systems,high level synthesis,hardware accelerator,multifunction
Architecture,Computer science,Parallel computing,High-level synthesis,Real-time computing,Computer hardware,Embedded system
Conference
ISBN
Citations 
PageRank 
1-59593-370-0
14
0.69
References 
Authors
21
4
Name
Order
Citations
PageRank
Kevin Fan133520.29
Manjunath Kudlur2199771.21
Hyunchul Park334117.56
Scott Mahlke44811312.08