Paper Info
Title
Clock skew scheduling for soft-error-tolerant sequential circuits
Abstract
Soft errors have been a critical reliability concern in nanoscale integrated circuits, especially in sequential circuits where a latched error can be propagated for multiple clock cycles and affect more than one output, more than once. This paper presents an analytical methodology for enhancing the soft error tolerance of sequential circuits. By using clock skew scheduling, we propose to minimize the probability of unwanted transient pulses being latched and also prevent latched errors from propagating through sequential circuits repeatedly. The overall methodology is formulated as a piecewise linear programming problem whose optimal solution can be found by existing mixed integer linear programming solvers. Experiments reveal that 30-40% reduction in the soft error rate for a wide range of benchmarks can be achieved.
Year
DOI
Venue
2010
10.1109/DATE.2010.5456956
DATE
Keywords
Field
DocType
sequential circuits,integrated circuit reliability,clock cycle,overall methodology,integer programming,circuit optimisation,fault tolerance,linear programming,clock skew scheduling,sequential circuit,clocks,soft-error-tolerant sequential circuit,mixed integer linear programming,analytical methodology,piecewise linear programming,soft error rate,unwanted transient pulse,piecewise linear techniques,flip-flops,multiple clock cycle,critical reliability concern,soft error tolerance,soft error,latched error,probability,clock skew,dithering,piecewise linear,logic circuits,integer linear programming,integrated circuit,logic gates,degradation,scheduling
Logic gate,Sequential logic,Soft error,Computer science,Real-time computing,Integer programming,Linear programming,Cycles per instruction,Integrated circuit,Piecewise linear function
Conference
ISSN
ISBN
Citations 
1530-1591
978-1-4244-7054-9
2
PageRank 
References 
Authors
0.36
15
2
Name
Order
Citations
PageRank
Kai-Chiang Wu111313.98
Diana Marculescu22725223.87