Paper Info
Title
A pattern matching algorithm for verification and analysis of very large IC layouts
Abstract
We propose a simple, isometry invariant pattern matching algorithm for an effective data reduction useful in layout-related data processing of very complex IC designs. The repeatable geometrical features and attributes are stored in a pattern database. Original pattern instance, or its geometrical attributes, may be quickly regenerated based both on the information stored within the pattern and position of the pattern instance. We also show preliminary results of analysis of the state-of-the-art ICs which suggest that the diversity of patterns does not significantly increase with the increase of chip size.
Year
DOI
Venue
1998
10.1145/274535.274554
ISPD
Keywords
Field
DocType
layout-related data,pattern database,pattern instance,original pattern instance,isometry invariant pattern,effective data reduction,large ic layout,chip size,geometrical attribute,repeatable geometrical feature,complex ic design,pattern matching,relational data,chip,data reduction
String searching algorithm,Data processing,Pattern recognition,Computer science,Isometry,Chip size,Invariant (mathematics),Artificial intelligence,Data reduction
Conference
ISBN
Citations 
PageRank 
1-58113-021-X
6
1.12
References 
Authors
8
3
Name
Order
Citations
PageRank
Mariusz Niewczas1122.28
Wojciech Maly21976352.57
Andrzej Strojwas3144.18