Title
On Using Efficient Test Sequences for BIST
Abstract
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.
Year
DOI
Venue
2002
10.1109/VTS.2002.1011126
VLSI Test Symposium, 2002.
Keywords
Field
DocType
efficient test sequences,good coverage,random single input change,arbitrary misbehavior,different fault type,high defect coverage,comprehensive test vector generation,digital system,single on-chip test generation,system on a chip,system testing,semiconductor device modeling,chip,sequences
Automatic test pattern generation,Test vector generation,Fault coverage,Computer science,Automatic test equipment,Logic testing,Real-time computing,Electronic engineering,Test compression,Computer engineering,Built-in self-test
Conference
ISSN
Citations 
PageRank 
1093-0167
12
0.68
References 
Authors
10
5
Name
Order
Citations
PageRank
David R. Foster1302.57
P. Girard247841.91
C. Landrault3523.07
S. Pravossoudovitch468954.12
A. Virazel516923.25