Name
Abstract | ||
|---|---|---|
In recent years a number of methods for designing self-timed circuits have been proposed. As a first step towards a comparison of these, we have designed a vector-multiplier using three of the published approaches: a Caltech design [5, 7], a multi-ring design [10, 11] (both are delay-insensitive circuits using four-phase handshaking and dual-rail encoding of data), and a micropipeline design [12, 8] (using a two-phase bundled-data protocol). Furthermore, a synchronous design of the same multiplier has been made. All the designs have been completed down to the layout level, and chips for two of the self-timed designs have been fabricated and tested. Based on these design experiments we report both quantitative and qualitative comparisons. |
Year | Venue | Keywords |
|---|---|---|
1993 | Asynchronous Design Methodologies | self-timed multipliers |
Field | DocType | Volume |
Computer science,Arithmetic | Conference | 28 |
ISSN | ISBN | Citations |
0926-5473 | 0-444-81599-6 | 14 |
PageRank | References | Authors |
4.76 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jens Sparsø | 1 | 453 | 52.97 |
| Christian D. Nielsen | 2 | 50 | 10.08 |
| lars nielsen | 3 | 160 | 108.97 |
| Jørgen Staunstrup | 4 | 248 | 75.43 |