Name
Abstract | ||
|---|---|---|
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by variability because of its exponential dependence on the highly varying transistor channel length and threshold voltage. This paper describes the new technology mapping algorithm that performs library binding to maximize parametric yield limited both by timing and power constraints. This is the first work that rigorously treats variability in circuit leakage power and delay within logic synthesis. Experiments show that moving the concerns about variability into logic synthesis is justified. The results on industrial and public benchmarks indicate that, on avenge, the reduction in stand-by power can be up to 26% and can be as high as 50% for some benchmarks. The reduction is purely due to a more effective decision-making of the mapping algorithm, and is achieved without a timing parametric yield loss. Alternatively, the algorithm leads to the delay reduction of up to 17%, with a 10% avenge possible reduction across the benchmarks, for stringent leakage constraints at a fixed yield level. Parametric yield at a fixed leakage target can also be substantially increased. In some examples, the statistical mapper leads to a 80% yield at the leakage value for which the deterministic mapper guaranteed only a 50% yield. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ICCAD.2005.1560121 | ICCAD |
Keywords | Field | DocType |
fixed leakage target,leakage power constraint,timing parametric yield loss,parametric yield,statistical technology mapping,substantial parametric yield loss,leakage value,leakage power,fixed yield level,circuit leakage power,logic synthesis,integrated circuit design,logic design,statistical analysis,threshold voltage | Logic synthesis,Exponential function,Leakage (electronics),Computer science,Communication channel,Electronic engineering,Real-time computing,Integrated circuit design,Parametric statistics,Transistor,Threshold voltage | Conference |
ISSN | ISBN | Citations |
1063-6757 | 0-7803-9254-X | 4 |
PageRank | References | Authors |
0.48 | 21 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Singh | 1 | 42 | 8.59 |
| Mani, M. | 2 | 4 | 0.48 |
| M. Orshansky | 3 | 14 | 1.14 |