Name
Abstract | ||
|---|---|---|
Historically, Back End of Line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1065579.1065778 | DAC |
Keywords | Field | DocType |
hardware,signal integrity,process variation,parasitic capacitance,rc circuits,interconnect,extraction,crosstalk,copper,etching,random process | Parasitic capacitance,Capacitance,Computer science,Signal integrity,Back end of line,Electronic engineering,RC circuit,Process variation,Circuit performance,Interconnection | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-59593-058-2 | 7 |
PageRank | References | Authors |
0.60 | 2 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| N. S. Nagaraj | 1 | 86 | 17.37 |
| Tom Bonifield | 2 | 19 | 2.97 |
| Abha Singh | 3 | 19 | 2.97 |
| Clive Bittlestone | 4 | 22 | 3.77 |
| Usha Narasimha | 5 | 35 | 5.81 |
| Viet Le | 6 | 16 | 2.25 |
| Anthony M. Hill | 7 | 35 | 6.58 |