Name
Abstract | ||
|---|---|---|
This paper proposes an isometry invariant pattern matching algorithm tailored for layout-related processing of complex integrated circuit (IC) designs. This algorithm applies signatures identifying contour equivalence classes. The proposed algorithm is useful for data reduction purposes by enabling construction of a database of repeatable IC primitives. We show several results of analysis of the state-of-the-art ICu0027s which suggest that the diversity of patterns does not significantly increase with increasing chip size. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/43.752932 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
contour equivalence class,repetitive pattern,isometry invariant pattern,data reduction purpose,state-of-the-art IC,layout-related processing,enabling construction,large IC layout,complex integrated circuit,chip size,repeatable IC primitive,proposed algorithm | Journal | 18 |
Issue | ISSN | Citations |
4 | 0278-0070 | 1 |
PageRank | References | Authors |
0.81 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Niewczas | 1 | 1 | 0.81 |
| Wojciech Maly | 2 | 1976 | 352.57 |
| A. J. Strojwas | 3 | 242 | 58.96 |