Name
Abstract | ||
|---|---|---|
This paper presents a heterogeneous multimedia processor for embedded media applications such as image processing, vision, 3-D graphics and augmented reality (AR), assuming integrated circuit (IC)-stacking on Si-interposer. This processor embeds reconfigurable output drivers for external memory interface to increase memory bandwidth even in a mobile environment. The implemented output driver reconfigures its driving strength according to channel loss between the implemented processor and the memory, so it enables high-speed data communication while achieving $8\\times$ higher memory bandwidth compared to previous embedded media processors. The implemented processor includes three main programmable intellectual properties, mode-configurable vector processing units (MCVPUs), a unified filtering unit (UFU), and a unified shader. MCVPUs have 32 integer (16 bit) cores in order to support dual-mode operations between image-level processing and graphics processing. This mode-configuration enables a frame-level pipelining in AR application, so the proposed processor achieves $1.7\\times$ higher frame rate compared to the sequential AR processing. UFU supports 16 types of filtering operations only with a single instruction. Most image-level processing consists of various types of filtering operations, so UFU can improve media processing performance and energy-efficiency. UFU also supports texture filtering which is performance bottleneck of common graphics pipeline. A memory-access-efficient (off-chip memory) texturing algorithm named as an adaptive block selection is proposed to enhance texturing performance in 3-D graphics pipeline. UFU has two-level on-chip memory hierarchies, a 512B level-0 (L0) data buffer, and an 8 kB level-1 (L1) static random-access memory (SRAM) cache. The small-sized L0 data buffer limits direct references to the large-sized L1 SRAM cache to reduce energy consumed in on-chip memories. Unified shader consists of four homogeneous scalar processing elements (SPEs) for geometry operations in 3-D graphics. Each SPE has single-precision floating-point data-paths, since precision of geometry operations in 3-D graphics is important in today's handheld devices (high resolution). The proposed media processor is fabricated in 0.13 $\\mu{\\rm m}$ CMOS technology with 4 mm $\\times\\,$4 mm chip size, and dissipates 275 mW for full AR operation. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TCSVT.2011.2171209 | IEEE Trans. Circuits Syst. Video Techn. |
Keywords | Field | DocType |
embedded systems,intellectual property,media,data buffer,three dimensional,mobile computing,pipelines,high resolution,memory bandwidth,handheld device,cmos integrated circuits,handheld devices,floating point,integrated circuit,integrated circuits,filtering,energy efficient,static random access memory,cmos technology,graphics,prototypes,computer graphics,media processor,external memory,energy efficiency,chip,augmented reality,unified shader,image processing,texture filtering,hardware | Media processor,Memory bandwidth,Graphics pipeline,Cache,Computer science,Unified shader model,Computer hardware,Vector processor,External memory interface,Multimedia,Texture mapping unit,Embedded system | Journal |
Volume | Issue | ISSN |
22 | 4 | 1051-8215 |
Citations | PageRank | References |
3 | 0.42 | 19 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyo-Eun Kim | 1 | 33 | 4.80 |
| Jae-Sung Yoon | 2 | 35 | 5.31 |
| Kyu-Dong Hwang | 3 | 17 | 2.67 |
| Young-Jun Kim | 4 | 13 | 2.09 |
| Junseok Park | 5 | 214 | 26.80 |
| Lee-Sup Kim | 6 | 707 | 98.58 |