Title | ||
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An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS |
Abstract | ||
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This paper presents an energy-efficient feature extraction accelerator design aimed at visual navigation. The hardware-oriented algorithmic modifications such as a circular-shaped sampling region and unified description are proposed to minimize area and energy consumption while maintaining feature extraction quality. A matched-throughput accelerator employs fully-unrolled filters and single-stream descriptor enabled by algorithm-architecture co-optimization, which requires lower clock frequency for the given throughput requirement and reduces hardware cost of description processing elements. Due to the large number of FIFO blocks, a robust low-power FIFO architecture for the ultra-low voltage (ULV) regime is also proposed. This approach leverages shift-latch delay elements and balanced-leakage readout technique to achieve 62% energy savings and 37% delay reduction. We apply these techniques to a feature extraction accelerator that can process 30 fps VGA video in real time and is fabricated in 28 nm LP CMOS technology. The design consumes 2.7 mW with a clock frequency of 27 MHz at Vdd = 470 mV, providing 3.5× better energy efficiency than previous state-of-the-art while extracting features from entire image. |
Year | DOI | Venue |
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2014 | 10.1109/JSSC.2014.2309692 | J. Solid-State Circuits |
Keywords | DocType | Volume |
lp cmos,energy savings,visual navigation,shift-latch delay elements,single-stream descriptor,balanced-leakage readout technique,near-threshold design,frequency 27 mhz,first-in first-out,size 28 nm,algorithm-architecture co-optimization,circular-shaped sampling region,fifo blocks,fully-unrolled filters,low-power electronics,low-power fifo architecture,pipeline,energy efficient dsp,matched-throughput accelerator,hardware-oriented algorithmic modifications,vga video,feature extraction,cmos logic circuits,logic design,delay reduction,shift-latch fifo,energy efficient full-frame feature extraction accelerator,power 2.7 mw,energy consumption,description processing elements,flip-flops,voltage 470 mv,energy efficiency,visualization,first in first out,low power electronics,vectors,algorithm design and analysis,detectors,navigation | Journal | 49 |
Issue | ISSN | Citations |
5 | 0018-9200 | 10 |
PageRank | References | Authors |
0.59 | 17 | 7 |
Name | Order | Citations | PageRank |
---|---|---|---|
Dongsuk Jeon | 1 | 183 | 21.01 |
Michael B. Henry | 2 | 71 | 9.93 |
Yejoong Kim | 3 | 276 | 31.29 |
Inhee Lee | 4 | 275 | 33.89 |
Zhengya Zhang | 5 | 502 | 48.41 |
David Blaauw | 6 | 8916 | 823.47 |
Dennis Sylvester | 7 | 5295 | 535.53 |