Name
Abstract | ||
|---|---|---|
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores embedded into a system on chip. The resulting test time of the system is evaluated considering the number of reused processors, the number of external interfaces, and power dissipation. Experimental results for a set of industrial examples based on the ITC'02 benchmarks show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/1016568.1016602 | SBCCI |
Keywords | Field | DocType |
cooperative use,test planning method,access mechanism,test time,test source,processor reuse,available processor,on-chip network,test parallelism,embedded processor,resulting test time,chip,embedded systems,network on chip,power dissipation,system on chip | Test plan,System on a chip,Reuse,Computer science,Dissipation,Network on a chip,Real-time computing,Embedded system | Conference |
ISBN | Citations | PageRank |
1-58113-947-0 | 11 | 0.74 |
References | Authors | |
14 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexandre M. Amory | 1 | 113 | 15.56 |
| Érika Cota | 2 | 53 | 3.87 |
| Marcelo Lubaszewski | 3 | 483 | 47.66 |
| Fernando Moraes | 4 | 720 | 43.62 |