Title
Bus Optimization for Low Power in High-Level Synthesis
Abstract
Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral level and the RT level of design. This paper addresses the problem of minimizing power dissipated in the switching of the buses in the high-level synthesis of data-dominated behavioral descriptions. Unlike the previous approaches in which the minimization of the power consumed in buses has not been considered until operation scheduling is completed, our approach integrates the bus binding problem into scheduling to exploit the impact of scheduling on the reduction of power dissipated on the buses more fully and effectively. We accomplish this by formulating the problem into a flow problem in a network, and devising an efficient algorithm which iteratively finds the maximum flow of minimum cost solutions in the network. Experimental results on a number of benchmark problems show that given resource and global timing constraints our designs axe 19.8% power-efficient over the designs produced by a random-move based solution, and 15.5% power-efficient over the designs by a clock-step based optimal solution.
Year
DOI
Venue
2003
10.1142/S0218126603000829
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
Keywords
Field
DocType
bus optimization,high-level synthesis,low-power design,scheduling
Computer science,Scheduling (computing),Flow (psychology),High-level synthesis,Electronic engineering,Exploit,Minification,Maximum flow problem,Operation scheduling,Binding problem
Journal
Volume
Issue
ISSN
12
1
0218-1266
Citations 
PageRank 
References 
1
0.48
7
Authors
2
Name
Order
Citations
PageRank
Sungpack Hong186433.20
Taewhan Kim21087113.31