Name
Abstract | ||
|---|---|---|
In this paper, we introduce a methodology for designing a system for face detection and its implementation on FPGA. The chosen face detection method is the well-known convolutional face finder (CFF) algorithm, which consists in a pipeline of convolutions and subsampling operations. Our goal is to define a parallel architecture able to process efficiently this algorithm. We present a dataflow based architecture algorithm adequation (AAA) methodology implemented using the SynDEx software, in order to find the best compromise between the processing power and functionality requirement of each processor element (PE), and the efficiency of algorithm parallelization. We describe a first implementation of a PE on a Virtex 4 FPGA using the DSP48 dedicated blocks. This PE is able to run at a maximum frequency of 352 MHz and occupies only 2% of a Virtex 4 SX35 device. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISCAS.2007.378647 | New Orleans, LA |
Keywords | Field | DocType |
convolutional codes,face recognition,field programmable gate arrays,parallel architectures,352 MHz,DSP48 dedicated blocks,FPGA,SynDEx software,Virtex 4 SX35 device,algorithm parallelization,architecture algorithm adequation methodology,convolutional face finder algorithm,face detection system,parallel architecture,processor element | Facial recognition system,Convolutional code,Computer science,Convolution,Field-programmable gate array,Dataflow,Software,Virtex,Face detection,Embedded system | Conference |
ISSN | ISBN | Citations |
0271-4302 | 1-4244-0921-7 | 4 |
PageRank | References | Authors |
0.56 | 7 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nicolas Farrugia | 1 | 21 | 4.16 |
| Franck Mamalet | 2 | 302 | 16.35 |
| Sébastien Roux | 3 | 42 | 5.81 |
| Fan Yang | 4 | 133 | 13.50 |
| Michel Paindavoine | 5 | 115 | 21.70 |