Name
Abstract | ||
|---|---|---|
This paper proposes a service-oriented reconfigurable co-processing architecture. The novelty of the architecture is to apply service-oriented concepts to system on chip (SoC) design paradigms and utilizes each processor and IP core as a function unit. Regarded as abstract instructions, tasks can be scheduled to IP core for parallel execution automatically. A uniform IP reconfiguration interface is provided to allow function units replacement at run-time. Neither the applications nor the tool chains need to be redesigned after hardware reconfiguration. To evaluate the SOA concepts, we implemented a prototype on a state-of-art Virtex5 FPGA board with IP cores implemented from EEMBC DENBench. The prototype and experimental results demonstrate it can support a range of hardware accelerators in an efficient manner. Furthermore, results also depict that the architecture takes moderate silicon area affordable power consumption. We believe the SOA approach opens a new direction to combine SOA concepts with reconfigurable computing hardware architectures. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/SCC.2012.72 | IEEE SCC |
Keywords | Field | DocType |
service-oriented reconfigurable co-processing architecture,reconfigurable ip cores,reconfigurable computing hardware architecture,virtex5 fpga board,ip core,system on chip,microprocessor chips,soc,soa concept,parallel execution,soa approach,reconfigurable architectures,system on chip design,system-on-chip,service-oriented concept,reconfigurable computing hardware architectures,soa concepts,eembc denbench,service-oriented architecture,integrated circuit design,co-processor,hardware reconfiguration,uniform ip reconfiguration interface,field programmable gate arrays,hardware accelerator,function unit,function units replacement,service-oriented,run-time reconfiguration,co processor,service oriented architecture,hardware,system on a chip,computer architecture | Architecture,Computer architecture,System on a chip,Computer science,Field-programmable gate array,Integrated circuit design,Coprocessor,Service-oriented architecture,Control reconfiguration,Reconfigurable computing,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4673-3049-7 | 12 | 0.69 |
References | Authors | |
4 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chao Wang | 1 | 372 | 62.24 |
| Xi Li | 2 | 202 | 36.61 |
| Peng Chen | 3 | 12 | 2.38 |
| Junneng Zhang | 4 | 97 | 8.85 |
| Xiaojing Feng | 5 | 62 | 5.69 |
| Xuehai Zhou | 6 | 37 | 6.89 |