Name
Abstract | ||
|---|---|---|
The main contribution of this paper is to propose an FPGA implementation of template matching using DSP slices. Template matching is a technique for finding small parts of an image which match a template image. In our approach, we use a pixel rearrangement technique that is a coarse-to-fine technique. Unlike ordinary coarse-to-fine techniques, it always can find a template image in a base image if the template image is included in the base image. In our implementation, we use multiple matching modules that compute similarity and work in parallel. In each matching module, we efficiently use embedded DSP slices on the Virtex-6 FPGA. We have implemented the template matching in a Xilinx Virtex-6 FPGA XC6VLX240T-FF1156. The implementation results show that it can be implemented in the FPGA with 352 DSP slices, 3 block RAMs and 455 CLBs. It runs in approximately 280MHz clock frequency. The computing time of our FPGA implementation is 348.88 and 3.66 times faster than that of CPU and GPU implementations, respectively. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/CANDAR.2013.61 | CANDAR |
Keywords | Field | DocType |
matching module,template image,gpu implementation,xilinx virtex-6 fpga,template matching,dsp slice,multiple matching module,base image,virtex-6 fpga,dsp slices,fpga implementation,field programmable gate arrays | Template matching,Digital signal processing,Block ram,Image matching,Computer science,Parallel computing,Parallel processing,Field-programmable gate array,Pixel,Computer hardware,Clock rate | Conference |
Citations | PageRank | References |
5 | 0.51 | 13 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kaoru Hashimoto | 1 | 5 | 0.51 |
| Yasuaki Ito | 2 | 511 | 60.47 |
| Koji Nakano | 3 | 1165 | 118.13 |