Name
Title | ||
|---|---|---|
Statistical Leakage Minimization Of Digital Circuits Using Gate Sizing, Gate Length Biasing, And Threshold Voltage Selection |
Abstract | ||
|---|---|---|
This paper dagger proposes a novel methodology for statistical leakage minimization of digital circuits. A function of mean and variance of the circuit leakage is minimized with constraint on alpha-percentile of the path delays using physical delay models fitted to a 90-nm industrial technology. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables can provide significant amount of power savings. The formulated leakage minimization problem is shown to be a multivariable convex optimization problem under specific variable transformations. We demonstrate that our statistical optimization can lead to more than 50% reduction in the 90-percentile leakage for a 6% increase in the required time constraint. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1166/jolpe.2006.065 | JOURNAL OF LOW POWER ELECTRONICS |
Keywords | Field | DocType |
Leakage Minimization, Statistical Optimization, Gate Sizing, Convex Optimization, Probability, Gate Length Biasing | Digital electronics,Leakage (electronics),Overdrive voltage,NAND gate,Electronic engineering,Minification,Engineering,Gate equivalent,Threshold voltage,Electrical engineering,Biasing | Journal |
Volume | Issue | ISSN |
2 | 2 | 1546-1998 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sarvesh Bhardwaj | 1 | 0 | 0.68 |
| Yu Cao | 2 | 329 | 29.78 |
| Sarma Vrudhula | 3 | 2380 | 180.63 |