Name
Title | ||
|---|---|---|
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers |
Abstract | ||
|---|---|---|
In this paper, a power management technique based on dynamic frequency scaling is proposed. The proposed technique targets digital receivers employing adaptive sampling. Such circuits over-sample the analogue input signal, in order to succeed timing synchronization. The proposed technique introduces power savings by forcing the receiver to operate only on the "correct" data for the time intervals during which synchronization is achieved. The simple architectural modifications, needed for the application of the proposed strategy, are described. As test-vehicle a number of FIR filters, which are the basic components of almost every digital receiver, are used. The experimental results prove that the application of the proposed technique introduces significant power savings, while negligibly increasing area and critical path. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1007/3-540-45373-3_6 | PATMOS |
Keywords | Field | DocType |
analogue input signal,timing synchronization,power management technique,power consumption,adaptive sampling,significant power saving,proposed technique,digital receiver,fir filter,power saving,proposed strategy,dynamic frequency scaling,digital receivers | Power management,Synchronization,Digital electronics,Adaptive sampling,Computer science,Electronic engineering,Dynamic frequency scaling,Critical path method,Finite impulse response,Energy consumption | Conference |
ISBN | Citations | PageRank |
3-540-41068-6 | 0 | 0.34 |
References | Authors | |
5 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| N. D. Zervas | 1 | 90 | 9.58 |
| S. Theoharis | 2 | 11 | 2.32 |
| A. P. Kakaroudas | 3 | 1 | 0.76 |
| george theodoridis | 4 | 67 | 14.19 |
| Dimitrios Soudris | 5 | 89 | 26.17 |
| Constantinos E. Goutis | 6 | 75 | 16.82 |